1. Field of the Invention
The present invention relates to a method of manufacturing a high frequency module and to the high frequency module. More particularly, the present invention relates to a method of manufacturing a high frequency module having a structure in which a component mounting surface of a unit substrate, on which an electronic component is mounted, is encapsulated (covered in a sealed condition) with an encapsulation layer made of an insulating material, and in which a conductive shield layer electrically conducted to a ground potential covers the encapsulation layer. The present invention also relates to the high frequency module manufactured by the above-mentioned manufacturing method.
2. Description of the Related Art
As one of high frequency modules, there is a high frequency module in which an electronic component is mounted on a component mounting surface of a substrate, the component mounting surface and the electronic component are encapsulated with an encapsulation layer made of, e.g., an insulating material, and a surface of the encapsulation layer (i.e., a module surface) is covered with a conductive shield layer made of an electroconductive material and electrically conducting the module surface to a ground potential, thereby reducing intrusion of electromagnetic waves from the outside and leakage of electroconductive waves to the outside.
As a method of manufacturing the high frequency module having such a structure, the following method is proposed (see Japanese Unexamined Patent Application Publication No. 2009-218484).
According to the method disclosed in Japanese Unexamined Patent Application Publication No. 2009-218484, as illustrated in FIG. 16, electronic components 102 and 103 are mounted on a collective substrate 110a, which is a collective body including a plurality of unit substrates 110 and electrodes (via conductors) 101 electrically conducted to a ground potential (ground electrode G), and a component mounting surface of the collective substrate 110a and the electronic components 102 and 103 are encapsulated with an encapsulation layer (encapsulation resin) 104.
Then, as illustrated in FIG. 17, the collective substrate 110a encapsulated with the encapsulation resin 104 is cut along a reference line S from the side containing the encapsulation layer (encapsulation resin) 104, thereby forming a half-cut groove 105 that penetrates through the encapsulation layer (encapsulation resin) 104 and that extends up to a position halfway the collective substrate 110a in the direction of thickness thereof. With the formation of the half-cut groove 105, each via conductor 101 is exposed at a lateral surface 105a and a bottom surface 105b of the half-cut groove 105 such that a contact area between the via conductor 101 and a conductive shield layer 106 (described below) can be sufficiently obtained.
Then, as illustrated in FIG. 18, the conductive shield layer 106 is formed such that it covers the encapsulation layer (encapsulation resin) 104 and it is electrically conducted to the via conductor 101 exposed at the lateral surface 105a and the bottom surface 105b of the half-cut groove 105.
Further, after carrying out various necessary steps, the collective substrate 110a is divided into individual unit substrates (electronic modules) 110.
In such a manner, the method of manufacturing the electronic module, disclosed in Japanese Unexamined Patent Application Publication No. 2009-218484, provides the electronic module in which the electronic components 102 and 103 are mounted on the substrate (unit substrate) 110, the electronic components 102 and 103 and the mounting surface for those electronic components are encapsulated with the encapsulation layer (encapsulation resin) 104, and the surface of the encapsulation layer (encapsulation resin) 104 is covered with the conductive shield layer that is electrically conducted to the ground potential.
Moreover, with the method disclosed in Japanese Unexamined Patent Application Publication No. 2009-218484, when the collective substrate 110a is half-cut, a lateral portion of the via conductor 101 is also partly cut such that a lateral surface 101a of the via conductor 101, which surface has been formed by the half-cutting, is exposed at the lateral surface 105a of the half-cut groove 105, and such that a horizontal surface 101b of the via conductor 101 (i.e., a horizontal surface of the via conductor, which surface has been formed by the half-cutting) is exposed at the bottom surface 105b of the half-cut groove 105. Therefore, a contact area between the conductive shield layer 106 and the via conductor 101 at the ground potential is increased and high reliability in electrical connection can be ensured with such a feature.
However, the method disclosed in Japanese Unexamined Patent Application Publication No. 2009-218484 has a problem in that, because the lateral surface 101a and the bottom surface 101b of the via conductor 101 are both exposed to increase the contact area between the conductive shield layer 106 and the via conductor 101, there is a risk that the via conductor 101 may slip off of the collective substrate 110a and fall into the half-cut groove 105. This gives rise to a problem of reducing reliability.
As another module manufacturing method, there is disclosed a method of manufacturing a circuit module, the method including the steps of half-cutting a collective substrate such that an inner electrode layer (in-plane electrode), which is disposed inside the collective substrate and which is held at a ground potential, is exposed at a lateral surface of a half-cut groove, and then connecting a conductive shield layer to the in-plane electrode exposed at the lateral surface of the half-cut groove (see Japanese Unexamined Patent Application Publication No. 2008-288610, FIG. 3).
However, the method disclosed in Japanese Unexamined Patent Application Publication No. 2008-288610 has the following problem. Because the thickness of the inner electrode layer (in-plane electrode) to be electrically conducted to the conductive shield layer is much smaller (thinner) than the depth of the half-cut groove, the inner electrode layer (in-plane electrode) cannot be exposed at the lateral surface of the half-cut groove in some cases depending on accuracy in depth size of the half-cut groove. For example, when the inner electrode layer (in-plane electrode) is formed at a position near a lower surface of the collective substrate, it is difficult to form the half-cut groove so as to not cut through the collective substrate and such that the inner electrode layer (in-plane electrode) is exposed at the lateral surface of the half-cut groove.
Another problem is that, even when the inner electrode layer (in-plane electrode) can be exposed at the lateral surface of the half-cut groove, reliability in electrical connection tends to become insufficient for the reason that the thickness of the inner electrode layer (in-plane electrode) is thin and hence the contact area between the conductive shield layer and the inner electrode layer (in-plane electrode) is small.